Automated test equipment (ATE) performs high speed testing on semiconductor devices to verify that the devices function properly during and after their manufacturing processes. Some ATE specializes in testing memory devices. Typical ATE systems input a pattern of test signals or data to a device under test (DUT), measure various test parameters relating to the input signals and compute an evaluation of the measurements and output data, which relate to analyzing the computed evaluation.
ATE systems may comprise automatic electromechanical probe, interface and adapter components. ATE systems may also comprise robotic handler components, which load and arrange multiple DUTs (e.g., mass-produced semiconductor devices) into the ATE at once, unload the tested devices and sort them by quality based on their test results. ATE improves test throughput and thus reduces the amount of time required to perform accurate testing, evaluation and handling of significant numbers of devices at once, which improves manufacturing yield and quality and reduces the costs of producing reliable semiconductor devices. An ATE system may specialize in testing memory.
ATE memory testing is performed using complex, computer-based test algorithms to detect memory faults during the final packaging stages of producing various types of memory devices. “Flash” memory comprises an erasable and reprogrammable non-volatile data storage medium with fast access time for computers, telephones, cameras and other portable or mobile electronics.
NAND (NOR/AND) type flash memory is page based, uses consecutive read operations in its input/output (I/O) ports and is less expensive and longer lasting (e.g., in relation to write and erase cycles) than NOR type flash memory, which uses random access and is typically used with computer BIOS (basic input/output system), firmware and other rarely updated applications. Redundancy analysis (RA), also referred to as “repair analysis,” of NAND flash memory comprises a significant function of their testing and feature of memory ATE, also referred to herein as a memory tester.
For example, NAND flash memories comprise at least a main block of memory cells and at least a spare block of memory cells, each of which functions with its own page buffer unit. The memory tester writes one or more given patterns of digital test signal data to each cell of the main cell block through the main page buffer and reads the test pattern back out therefrom to detect any errors, which would each indicate a defective cell. The spare block of memory cells provide redundancy for the cells of the main block of cells.
A repair controller is operable to map cell addresses in the spare block with the main block address of a failed cell therein and outputs a redundancy (e.g., repair) control signal to direct data writes to the spare cells, in lieu of writes to the failed main block cell to which the spare block address was mapped. The repair controller may be operable for optimizing the mapping between the main block and the spare block, thus increasing the degree of redundancy. RA thus allows a memory tester to evaluate and analyze the self-repair capability of NAND flash DUTs, which may significantly improve the yield and quality of their manufacture and production.
Test performance (e.g., speed and throughput) and cost comprise significant factors in RA. High NAND flash test throughput may be provided by tester-per-site ATE comprising multiple test sites, in each of which a single DUT is tested at a time. Each of the multiple test sites has its own independent test resources, which comprise a testing processor, an algorithmic test pattern generator, parametric measurement units, buffer memory and fail memory.
As the storage capacity of memory devices grows, the memory requirements of ATE also grow to store the data that is read out of a memory DUT. Large memory capacity however increases the costs of ATE. As newer memory devices evolve in general, their typical storage capacities have tended to increase significantly. The concomitant demand for more test data capture storage has thus become significant in the design and cost of conventional ATE.
Conventionally, RA is performed within a device main test program. This approach adds latency however, as the main test program devotes its resources to computing RA over a given cell before switching to the next cell to be tested. To reduce test latency and thus improve performance, some memory testers comprise a dedicated processor to compute the RA. However, this approach adds the cost of the additional RA processor to the expense of the testing.
Approaches described in this section may, but have not necessarily been conceived or pursued previously. Unless otherwise indicated, approaches mentioned (or issues identified in relation thereto) should not to be assumed as recognized in any prior art merely by inclusion in this section.